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utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 1 ? revision history revision description date rev.1.0 original june 20, 2002 rev.1.1 revised 1. ac timing requirements input pulse levels:0.8v~2.0v b 0.4v~2.4v tis(min):1, 1.5, 1.3, 2 b 2, 2.5, 2.5, 2.5ns tih(min):1, 0.8, 0.8, 0.8 b 1, 1, 1, 1ns 2. output load condition jul. 09, 2002 rev.1.2 add package outline dimension jul. 26, 2002 rev.1.3 1. page 1 : add access parameter into ?features? item -6 -7 -6 -7 unit t clk (min.) cl=2 - - b 10 10 ns t ac (max.) cl=2 - - b 6 6 ns t oh (min.) cl=2 - - b 3 3 ns 2. page 34,35 : add ?6ns,-7ns limits parameters feb. 10, 2003 rev.1.4 1. add operating temperature : commercial : 0 j ~70 j extended : -20 j ~80 j apr. 25, 2003
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 2 ? description ut52l0464 is organized as 4-bank x 4,194,304- word x 4-bit synchronous dram with lvttl interface and UT52L0864 is organized as 4-bank x 2,097,152-word x 8-bit and ut52l1664 is organized as 4-bank x 1,048,576-word x 16-bit. all inputs and outputs are referenced to the rising edge of clk. ut52l0464, UT52L0864 and ut52l1664 achieve very high speed data rates up to 166mhz, and are suitable for main memories or graphic memories in computer systems. features ut52l0464/0864/1664 item -6 -7 -7.5 -8 cl=2 10ns 10ns 10ns 10ns tclk clock cycle time (min.) cl=3 6ns 7ns 7.5ns 8ns tras active to precharge command preiod (min.) 42ns 45ns 45ns 48ns trcd row to column delay (min.) 18ns 20ns 20ns 20ns cl=2 6ns 6ns 6ns 6ns tac access time from clk (max.) cl=3 5ns 5.4ns 5.4ns 6ns trc ref/active command period (min.) 60ns 63ns 67.5ns 70ns ut52l0464 85ma 85ma 85ma 85ma UT52L0864 85ma 85ma 85ma 85ma icc1 operation current(single bank) (max.) ut52l1664 85ma 85ma 85ma 85ma icc6 self refresh current(max.) -6,-7,-7.5,8 1ma 1ma 1ma 1ma - single 3.3v 0.3v power supply - operating temperature : commercial : 0 j ~70 j extended : -20 j ~80 j - max. clock frequency -6:166mhz<3-3-3>/-7:143mhz<3-3-3>/-7.5:133mhz<3-3-3>/-8:100mhz<2-2-2> - fully synchronous operation referenced to clock rising edge - 4-bank operation controlled by ba0,ba1(bank address) - /cas latency- 2/3 (programmable) - burst length- 1/2/4/8/fp (programmable) - burst type- sequential and interleave burst (programmable) - byte control- dqml and dqmu (ut52l1664) - random column access - auto precharge / all bank precharge controlled by a10 - auto and self refresh - 4096 refresh cycles /64ms - lvttl interface - package 400-mil, 54-pin thin small outline (tsop ii) with 0.8mm lead pitch
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 3 ? pin configuration(top view) pin configuration (top view) 400mil 54pin tsop(ii) vss dq15 vssq dq13 vddq nc dq11 vssq dq9 vddq vss dqmu clk cke a9 a8 a7 a6 a5 nc a11 dq14 dq12 dq10 dq8 vss a4 vdd dq0 vddq dq2 vssq dq4 vddq dq6 vssq /we /ras dqml /cas vdd ba0(a13) /cs a10(ap) a0 a1 a2 dq1 dq3 dq5 dq7 ba1(a12) vdd a3 vdd dq0 vddq dq1 vssq dq2 vddq dq3 vssq /we /ras nc /cas vdd ba0(a13) /cs a10(ap) a0 a1 a2 nc nc nc nc ba1(a12) vdd a3 vdd nc vddq dq0 vssq nc vddq dq1 vssq /we /ras nc /cas vdd ba0(a13) /cs a10(ap) a0 a1 a2 nc nc nc nc ba1(a12) vdd a3 10 11 12 13 14 15 16 17 18 19 20 25 24 23 22 21 1 2 3 4 5 6 7 8 9 26 27 40 39 38 37 36 35 34 33 32 31 30 29 28 50 49 48 47 46 45 44 43 42 41 51 52 53 54 vss nc vssq dq3 vddq nc nc vssq dq2 vddq vss dqm clk cke a9 a8 a7 a6 a5 nc a11 nc nc nc nc vss a4 ut52l1664 UT52L0864 ut52l0464 a4 vss dq7 vssq dq6 vddq nc dq5 vssq dq4 vddq vss dqm clk cke a9 a8 a7 a6 a5 nc a11 nc nc nc nc vss
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 4 ? clk ?g master clock cke ?g clock enable /cs ?g chip select /ras ?g row address strobe /cas ?g column address strobe /we ?g write enable dq0-15 ?g data i/o dqm ?g output disable / write mask a0-11 ?g address input ba0,1 ?g bank address vdd ?g power supply vddq ?g power supply for output vss ?g ground vssq ?g ground for output
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 5 ? block diagram i/o buffer memory array 4096 x 512 x 8 cell array bank #0 memory array 4096 x 512 x 8 cell array bank #1 memory array 4096 x 512 x 8 cell array bank #2 memory array 4096 x 512 x 8 cell array bank #3 mode register control circuitry address buffer control signal buffer clock buffer dq0-7 a0-11 ba0,1 clk cke /cs /ras /cas /we dqm note ?g this figure shows the UT52L0864 the ut52l0464 configuration is 4096x1024x4 of cell array and dq0-3 the ut52l1664 configuration is 4096x256x16 of cell array and dq0-15
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 6 ? pin function clk input master clock: all other inputs are referenced to the rising edge of clk cke input clock enable: cke controls internal clock. when cke is low, internal clock for the following cycle is ceased. cke is also used to select auto / self-refresh. after self-refresh mode is started, cke becomes asynchronous input. self-refresh is maintained as long as cke is low. /cs input chip select: when /cs is high, any command means no operation. /ras, /cas, /we input combination of /ras, /cas, /we defines basic commands. a0-11 input a0-11 specify the row / column address in conjunction with ba0,1 the row address is specified by a0-11. the column address is specified by a0-9(x4)/a0-8(x8)/a0-7(x16). a10 is also used to indicate precharge option. when a10 is high at a read / write command, an auto precharge is performed. when a10 is high at a precharge command, all banks are precharged. ba0,1 input bank address: ba0,1 specifies one of four banks to which a command is applied. ba0,1 must be set with act, pre , read , write commands. dq0-3(x4), dq0-7(x8), dq0-15(x16) input/output data in and data out are referenced to the rising edge of clk. dqm(x4,x8), dqmu/l(x16) input din mask / output disable: when dqm(u/l) is high in burst write, din for the current cycle is masked. when dqm(u/l) is high in burst read, dout is disabled at the next but one cycle. vdd,vss power supply power supply for the memory array and peripheral circuitry. vddq,vssq power supply vddq and vssq are supplied to the output buffers only.
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 7 ? basic functions the ut52l0464,0864and 1664 provides basic functions, bank (row) activate, burst read / write, bank (row) precharge, and auto / self refresh. each command is defined by control signals of /ras, /cas and /we at clk rising edge. in addition to 3 signals, /cs ,cke and a10 are used as chip select, refresh option, and precharge option, respectively. to know the detailed definition of commands, please see the command truth table . clk /cs /ras /cas /we cke a10 chip select ?g l=select, h=deselect command command define basic command command refresh option @ refresh command precharge option @ precharge or read / write command activate (act) [/ras =l, /cas =/we =h] act command activates a row in an idle bank indicated by ba. read (read) [/ras =h, /cas =l, /we =h] read command starts burst read from the active bank indicated by ba. first output data appears after /cas latency. when a10 =h at this command, the bank is deactivated after the burst read (auto- precharge, reada). write (write) [/ras =h, /cas =/we =l] write command starts burst write to the active bank indicated by ba. total data length to be written is set by burst length. when a10 =h at this command, the bank is deactivated after the burst write (auto- precharge, writea). precharge (pre) [/ras =l, /cas =h, /we =l] pre command deactivates the active bank indicated by ba. this command also terminates burst read / write operation. when a10 =h at this command, all banks are deactivated (precharge all, prea ). auto-refresh (refa) [/ras =/cas =l, /we =cke =h] refa command starts auto-refresh cycle. refresh address including bank address are generated internally. after this command, the banks are precharged automatically.
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 8 ? command truth table command mnemonic cke n-1 cke n /cs /ras /cas /we ba0,1 a11 a10 a0-9 deselect desel h x h x x x x x x x no operation nop h x l h h h x x x x row address entry & bank active act h x l l h h v v v v single bank precharge pre h x l l h l v x l x precharge all banks prea h x l l h l x x h x column address entry & write write h x l h l l v v l v column address entry & write with auto-precharge writea h x l h l l v v h v column address entry & read read h x l h l h v v l v column address entry & read with auto-precharge reada h x l h l h v v h v auto-refresh refa h h l l l h x x x x self-refresh entry refs h l l l l h x x x x l h h x x x x x x x self-refresh exit refsx l h l h h h x x x x burst terminate tbst h x l h h l x x x x mode register set mrs h x l l l l l l l v*1 h=high level, l=low level, v=valid, x=don?t care, n=clk cycle number note: 1. a7-a9=0, a0-a6=mode address
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 9 ? function truth table current state /cs /ras /cas /we address command action idle h x x x x desel nop l h h h x nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act bank active, latch ra l l h l ba, a10 pre / prea nop*4 l l l h x refa auto-refresh*5 l l l l op-code, mode-add mrs mode register set*5 row active h x x x x desel nop l h h h x nop nop l h h l x tbst nop l h l h ba, ca, a10 read / reada begin read, latch ca, determine auto-precharge l h l l ba, ca, a10 write / writea begin write, latch ca, determine auto-precharge l l h h ba, ra act bank active, illegal*2 l l h l ba, a10 pre / prea precharge/ precharge all l l l h x refa illegal l l l l op-code, mode-add mrs illegal
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 10 ? function truth table (continued) current state /cs /ras /cas /we address command action read h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x tbst terminate burst l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto-precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto-precharge*3 l l h h ba, ra act bank active, illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal write h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x tbst terminate burst, latch ca, begin l h l h ba, ca, a10 read / reada terminate burst, latch ca, begin read, determine auto-precharge*3 l h l l ba, ca, a10 write / writea terminate burst, latch ca, begin write, determine auto-precharge*3 l l h h ba, ra act bank active, illegal*2 l l h l ba, a10 pre / prea terminate burst, precharge l l l h x refa illegal l l l l op-code, mode-add mrs illegal
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 11 ? function truth table (continued) current state /cs /ras /cas /we address command action h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal read with auto precharge l l l l op-code, mode-add mrs illegal h x x x x desel nop(continue burst to end) l h h h x nop nop(continue burst to end) l h h l x tbst illegal l h l h ba, ca, a10 read / reada illegal l h l l ba, ca, a10 write / writea illegal l l h h ba, ra act bank active / illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal write with auto precharge l l l l op-code, mode-add mrs illegal
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 12 ? function truth table (continued) current state /cs /ras /cas /we address command action h x x x x desel nop(idle after trp) l h h h x nop nop(idle after trp) l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea nop*4(idle after trp) l l l h x refa illegal pre- charging l l l l op-code, mode-add mrs illegal h x x x x desel nop(row active after trcd) l h h h x nop nop(row active after trcd) l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal row activating l l l l op-code, mode-add mrs illegal
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 13 ? function truth table (continued) current state /cs /ras /cas /we address command action h x x x x desel nop l h h h x nop nop l h h l x tbst illegal*2 l h l x ba, ca, a10 read / write illegal*2 l l h h ba, ra act illegal*2 l l h l ba, a10 pre / prea illegal*2 l l l h x refa illegal wtite recovering l l l l op-code, mode-add mrs illegal h x x x x desel nop(idle after trc) l h h h x nop nop(idle after trc) l h h l x tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal refreshing l l l l op-code, mode-add mrs illegal
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 14 ? function truth table (continued) current state /cs /ras /cas /we address command action h x x x x desel nop(idle after trsc) l h h h x nop nop(idle after trsc) l h h l x tbst illegal l h l x ba, ca, a10 read / write illegal l l h h ba, ra act illegal l l h l ba, a10 pre / prea illegal l l l h x refa illegal mode register setting l l l l op-code, mode-add mrs illegal
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 15 ? function truth table for cke current state cke n-1 cke n /cs /ras /cas /we add action h x x x x x x invalid l h h x x x x exit self-refresh (idle after trc) l h l h h h x exit self-refresh (idle after trc) l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self- refresh*1 l l x x x x x nop (maintain self-refresh) h x x x x x x invalid l h x x x x x exit power down to idle power down l l x x x x x nop (maintain power down) h h x x x x x refer to function truth table h l l l l h x enter self-refresh h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l x x x illegal all banks idle*2 l x x x x x x refer to current state =power down h h x x x x x refer to function truth table h l x x x x x begin clk susspend at next cycle*3 l h x x x x x exit clk susspend at next cycle*3 any state other than listed above l l x x x x x maintain clk suspend abbreviations: h=high level, l=low level, x=don't care notes: 1. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit. 2. power-down and self-refresh can be entered only from the all banks idle state. 3. must be legal command.
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 16 ? simplified state diagram idle self refresh auto refresh power down mode register set row active writea reada pre charge clk suspend power on refs refsx power applied automatic sequence command sequence pre writea writea pre pre pre reada read term write act ckel ckeh ckel ckeh mrs write suspend writea suspend reada suspend read suspend write read ckeh ckel ckeh ckel ckel ckeh ckel ckeh reada writea read write term reada refa
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 17 ? power on sequence before starting normal operation, the following power on sequence is necessary to prevent a sdram from damaged or malfunctioning. 1. apply power and start clock. attempt to maintain cke high, dqm high and nop condition at the inputs. 2. maintain stable power, stable clock, and nop input conditions for a minimum of 200s. 3. issue precharge commands for all banks. (pre or prea) 4. after all banks become idle state (after trp), issue 8 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. after these sequence, the sdram is idle state and ready for normal operation. mode register burst length, burst type and /cas latency can be programmed by setting the mode register (mrs). the mode register stores these data until the next mrs command, which may be issued when all banks are in idle state. after trsc from a mrs command, the sdram is ready for new command. clk /cs /ras /cas /we ba0,1 a11-a0 v ba0 ba1 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 wm 0 0 ltmode bt bl write mode burst write single write 0 1 latency mode cl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 3 /cas latency r r 2 r r r r burst length bl 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 8 bt=0 1 2 4 r r r fp 8 bt=1 1 2 4 r r r r burst type sequential interleaved 0 1 r : reserved for future use fp : full page
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 18 ? y y q0 q1 q2 q3 d0 d1 d2 d3 clk command address dq /cas latency burst length burst length burst type cl=3 bl=4 read write initial address bl column addressing a2 a1 a0 sequential interleaved 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 8 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 - 0 0 0 1 2 3 0 1 2 3 - 0 1 1 2 3 0 1 0 3 2 - 1 0 2 3 0 1 2 3 0 1 - 1 1 4 3 0 1 2 3 2 1 0 - - 0 0 1 0 1 - - 1 2 1 0 1 0
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 19 ? operational description bank activate the sdram has four independent banks. each bank is activated by the act command with the bank addresses (ba0,1). a row is indicated by the row addresses a0-11. the minimum activation interval between one bank and the other bank is trrd. maximum 2 act commands are allowed within trc , although the number of banks which are active concurrently is not limited. precharge the pre command deactivates the bank indicated by ba0,1. when multiple banks are active, the precharge all command (prea, pre + a10=h) is available to deactivate them at the same time. after trp from the precharge, an act command to the same bank can be issued. read after trcd from the bank activation, a read command can be issued. 1st output data is available after the /cas latency from the read, followed by (bl -1) consecutive data when the burst length is bl. the start address is specified by a0-a9(x4), a0-8(x8), a0-7 (x16) , and the address sequence of burst data is defined by the burst type. a read command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous output data by interleaving the multiple banks. when a10 is high at a read command, the auto-precharge (reada) is performed. any command (read, write, pre, tbst, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge starts at bl after reada. (need to keep tras min.) the next act command can be issued after (bl + trp) from the previous reada. bank activation and precharge all (bl=4, cl=3) xa clk command a0-9 act act a10 a11 ba0,1 dq act read pre xb y xb xb xb 01 1 xb 0 01 00 xb qa0 qa1 qa2 qa3 trcmin 2 act command / trcmin trrd xa xa 00 trcd tras trp prevharge all
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 20 ? multi bank interleaving read (bl=4, cl=3) xa clk command a0-9 act a10 a11 ba0,1 dq qa0 qa1 qa2 qa3 xa xa 00 trcd burst length cas latency act xb xb 10 xb read y 0 00 y read 0 10 pre 0 00 qb0 qb1 qb2 read with auto-precharge (bl=4, cl=3) clk command a0-9 a10 a11 ba0,1 dq read y 1 00 xa act xa xa 00 xa act xa xa 00 qa0 qa1 qa2 qa3 trcd bl trp internal precharge start bl + trp read auto-precharge timing (bl=4) clk command dq bl qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 read act dq cl=2 cl=3 internal precharge start timing
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 21 ? write after trcd from the bank activation, a write command can be issued. 1st input data is set at the same cycle as the write. following (bl -1) data are written into the ram, when the burst length is bl. the start address is specified by a0- a9(x4), a0-8(x8), a0-7(x16) and the address sequence of burst data is defined by the burst type. a write command may be applied to any active bank, so the row precharge time (trp) can be hidden behind continuous input data by interleaving the multiple banks. from the last input data to the pre command, the write recovery time (twr) is required. when a10 is high at a write command, the autoprecharge (writea) is performed. any command (read, write, pre, tbst, act) to the same bank is inhibited till the internal precharge is complete. the internal precharge begins at twr after the last input data cycle. (need to keep tras min.) the next act command can be issued after trp from the internal precharge timing. . write with auto-precharge (bl=4) clk command a0-9 a10 a11 ba0,1 dq xa xb act xb xb da1 10 write y 0 da0 00 write y db0 10 db1 da3 da2 db3 db2 0 pre 0 00 xa act xa 00 0 pre 0 10 trcd trcd 0 multi bank interleaving write (bl=4) clk command a0-9 a10 a11 ba0,1 dq da1 write y 1 da0 00 da3 da2 trcd xa xa act xa 00 xa xa act xa 00 trp twr internal precharge starts
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 22 ? burst interruption [ read interrupted by read ] burst read operation can be interrupted by new read of any bank. random column access is allowed read to read interval is minimum 1 clk. read interrupted by read (bl=4, cl=3) clk command a0-9 a10 a11 ba0,1 dq yi read 0 00 yj read 0 00 yk read 0 10 yl read 0 01 qai0 qaj0 qaj1 qbk0 qbk1 qbk2 qal0 qal1 qal2 qal3 [ read interrupted by write ] burst read operation can be interrupted by write of any bank. random column access is allowed. in this case, the dq should be controlled adequately by using the dqm to prevent the bus contention. the output is disabled automatically 1 cycle after write assertion. read interrupted by write (bl=4, cl=3) clk command a0-9 a10 a11 ba0,1 yi read 0 00 yj write 0 00 qai0 q daj0 daj1 daj2 daj3 d dqm contorl write contorl dqm
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 23 ? [ read interrupted by precharge ] burst read operation can be interrupted by precharge of the same bank . read to pre interval is minimum 1 clk. a pre command to output disable latency is equivalent to the /cas latency. as a result, read to pre interval determines valid data length to be output. the figure below shows examples of bl=4. read interrupted by precharge (bl=4) clk command read command read dq dq command q0 dq command read q0 q1 dq q0 q1 dq command read q0 dq command read q0 q1 q2 read q0 q1 pre pre pre pre pre pre q2 cl=3 cl=2
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 24 ? [read interrupted by burst terminate] similarly to the precharge, a burst terminate command can interrupt the burst read operation and disable the data output. the terminated bank remains active. read to tbst interval is minimum 1 clk. a tbst command to output disable latency is equivalent to the /cas latency. read interrupted by terminate (bl=4) clk command read command read dq dq command q0 dq command read q0 q1 dq q0 q1 dq command read q0 dq command read q0 q1 q2 read q0 q1 tbst tbst tbst tbst tbst tbst q2 cl=3 cl=2
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 25 ? [ write interrupted by write ] burst write operation can be interrupted by new write of any bank. random column access is allowed. write to write interval is minimum 1 clk. write interrupted by write (cl=3,bl=4) clk command a0-9 a10 a11 ba0,1 dq yi write 0 00 yj write 0 00 yk write 0 10 yl write 0 00 dai0 daj0 daj1 dbk0 dbk1 dbk2 dal0 dal1 dal2 dal3 [ write interrupted by read ] burst write operation can be interrupted by read of the same or the other bank. random column access is allowed. write to read interval is minimum 1 clk. the input data on dq at the interrupting read cycle is "don't care". write interrupted by read (cl=3,bl=4) clk command a0-9 a10 a11 ba0,1 qaj0 qaj1 dbk0 dbk1 dq dqm yi write 0 00 yj read 0 00 yk write 0 10 yl read 0 00 dai0 qal0
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 26 ? [write interrupted by precharge] burst write operation can be interrupted by precharge of the same bank.write recovery time(twr) is required from the last data to pre command. during write recovery, data inputs must be masked by dqm. write interrupted by precharge (bl=4) clk command a0-9,11 a10 xa act 0 xa act 0 pre ba0,1 00 00 dqm dq ya write 0 00 00 0 da0 da1 twr trp [write interrupted by burst terminate] burst terminate command can terminate burst write operation.in this case, the write recovery time is not required and the bank remains active. write to tbst interval is minimum 1 clk. write interrupted by terminate (bl=4) clk command a0-9,11 a10 xa act 0 yb write 0 tbst ba0,1 00 00 ya write 0 00 dq da0 da1 db0 db1 db2 db3
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 27 ? [write with auto-precharge interrupted by write or read to another bank] burst write with auto-precharge can be interrupted by write or read to another bank. next act command can be issued after trp. auto-precharge interruption by a command to the same bank is inhibited. write with auto-precharge interrupted by write to another bank (bl=4) clk command a0-9,11 a10 ya write 1 ba0,1 00 yb write 0 10 xa act xa 00 dq da0 da1 db0 db1 db2 db3 bl trp twr auto-precharge interrupted activate write with auto-precharge interrupted by read to another bank (cl=2,bl=4) clk command a0-9,11 a10 ya write 1 ba0,1 00 yb read 0 10 xa act xa 00 dq da0 da1 bl trp twr auto-precharge interrupted activate qb0 qb1 qb2 qb3
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 28 ? [read with auto-precharge interrupted by read to another bank] burst read with auto-precharge can be interrupted by write or read to another bank. next act command can be issued after trp. auto-precharge interruption by a command to the same bank is inhibited. read with auto-precharge interrupted by read to another bank (cl=2,bl=4) clk command a0-9,11 a10 ya read 1 ba0,1 00 yb read 0 10 dq qa0 qa1 bl trp auto-precharge interrupted activate qb0 qb1 qb2 qb3 xa act xa 00 [full page burst] full page burst length is available for only the sequential burst type. full page burst read or write is repeated untill a precharge or a burst terminate command is issued. in case of the full page burst, a read or write with auto-precharge command is illegal. [single write] when single write mode is set, burst length for write is always one, independently of burst length defined by (a2-0).
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 29 ? auto refresh single cycle of auto-refresh is initiated with a refa (/cs= /ras= /cas= l, /we= /cke= h) command. the refresh address is generated internally. 4096 refa cycles within 64ms refresh 64m bit memory cells. the auto-refresh is performed on 4 banks concurrently. before performing an auto-refresh, all banks must be in the idle state. auto-refresh to auto-refresh interval is minimum trc. any command must not be supplied to the device before trc from the refa command. auto-refresh clk /cs /ras /cas /we cke nop or deselect minimum trfc auto refresh on all banks auto refresh on all banks a0-11 ba0,1
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 30 ? self refresh self-refresh mode is entered by issuing a refs command (/cs= /ras= /cas= l, /we= h, cke= l). once the self-refresh is initiated, it is maintained as long as cke is kept low. during the self-refresh mode, cke is asynchronous and the only enabled input ,all other inputs including clk are disabled and ignored, so that power consumption due to synchronous inputs is saved. to exit the self-refresh, supplying stable clk inputs, asserting desel or nop command and then asserting cke=h. after trc from the 1st clk egde following cke=h, all banks are in the idle state and a new command can be issued, but desel or nop commands must be asserted till then. self-refresh clk stable clk /ras /cas /we cke a0-11 ba0,1 auto refresh entry /cs x 00 nop self refresh exit new command minimum trfc for recovery
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 31 ? clk suspend cke controls the internal clk at the following cycle. figure below shows how cke works. by negating cke, the next internal clk is suspended. the purpose of clk suspend is power down, output suspend or input suspend. cke is a synchronous input except during the self-refresh mode. clk suspend can be performed either when the banks are active or idle. a command at the suspended cycle is ignored. ext.clk cke int.clk tih tis tih tis power down by cke clk cke command active powen down act nop nop nop cke command standby powen down pre nop nop nop dq suspend by cke(cl=2) clk cke command write read dq d0 d1 d2 d3 q0 q1 q2 q3
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 32 ? dqm control dqm is a dual function signal defined as the data mask for writes and the output disable for reads. during writes, dqm(u,l) masks input data word by word. dqm(u,l) to write mask latency is 0. during reads, dqm(u,l) forces output to hi-z word by word. dqm(u,l) to output hi-z latency is 2. dqm function(cl=3) clk dq d0 d2 d3 q0 q1 q3 command write read dqm masked by dqm(u,l)=h disable by dqm(u,l)=h
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 33 ? absolute maximum ratings symbol parameter conditions ratings unit vdd supply voltage with respect to vss -0.5-4.6 v vddq supply voltage for output with respect to vssq -0.5-4.6 v vi input voltage with respect to vss -0.5-4.6 v vo output voltage with respect to vssq -0.5-4.6 v io output current 50 ma pd power dissipation ta=25 j 1000 mw commercial 0-70 j topr operating temperature extended -20-80 j tstg storage temperature -65-150 j recommended operating conditions limits symbol parameter min. typ. max. unit vdd supply voltage 3.0 3.3 3.6 v vss supply voltage 0 0 - v vddq supply voltage for output 3.0 3.3 3.6 v vssq supply voltage for output 0 0 0 v vih* 1 high-level input voltage all inputs 2.0 - vddq+0.3 v vil* 2 low-level input voltage all inputs -0.3 - 0.8 v notes: 1. vih(max)=5.5v for pulse width less than 10ns. 2. vil(min)=-1.0v for pulse width less than 10ns. capacitance (vdd=vddq=3.30.3v,vss=vssq=0v,unless otherwise noted) limits(max.) symbol patameter test condition limits(min.) -6,-7 -7.5,-8 unit ci(a) input capacitance,address pin 2.5 3.8 5.0 pf ci(c) input capacitance,contorl pin 2.5 3.8 5.0 pf ci(k) input capacitance, clk pin 2.5 3.5 4.0 pf ci/o input capacitance, i/o pin @1mhz 1.4v bias 200mv swing vcc=3.3v 4.0 6.5 6.5 pf
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 34 ? average supply current from vdd (vdd=vddq=3.30.3v,vss=vssq=0v,unless otherwise noted) limits(max.) item symbol test conditions organization -6 -7 -7.5 -8 unit x4 85 85 85 85 ma x8 85 85 85 85 ma operating current icc1 trc=min,tclk=min, bl=1,iol=0ma x16 85 85 85 85 ma icc2n cke=vihmin tclk=15ns x4/x8/x16 20 20 20 20 ma precharge standby current in non- power down mode icc2ns cke=vihmin tclk=vilmax(fixed) x4/x8/x16 15 15 15 15 ma icc2p cke=vilmax tclk=15ns(note) x4/x8/x16 2 2 2 2 ma precharge standby current in power down mode icc2ps cke=vilmax tclk=vilmax(fixed) x4/x8/x16 1 1 1 1 ma icc3n cke=/cs=vihmin tclk=15ns(note) x4/x8/x16 30 30 30 30 ma active stnadby current icc3ns cke=vihmin tclk=vilmax(fixed) x4/x8/x16 25 25 25 25 ma x4 100 100 100 100 ma x8 100 100 100 100 ma burst current icc4 all bank active tclk=min bl=4,cl=3,iol=0ma x16 100 100 100 100 ma auto-refresh current icc5 trc=min,tclk=min x4/x8/x16 130 130 130 130 ma self-refresh current icc6 cke<0.2v x4/x8/x16 6,7,7.5,8 1 1 1 1 ma note: 1. icc(max)is specified at the output open condition. 2. input signals are changed one time during 30ns. ac operating conditions and characteristics (vdd=vddq=3.30.3v,vss=vssq=0v,unless otherwise noted) limits symbol parameter test conditions min. max. unit voh(dc) high-level output voltage(dc) ioh=-2ma 2.4 v vol(dc) low-level output voltage(dc) iol=2ma 0.4 v ioz off-state output current q floatomg vo=0--vddq -5 5 a ii input current vih=0--vddq+0.3v -5 5 a
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 35 ? ac timing requirements (vdd=vddq=3.30.3v,vss=vssq=0v,unless otherwise noted) input pulse levels:0.4v-2.4v input timing measurement level:1.4v limits -6 -7 -7.5 -8 symbol parameter min. max. min. max. min. max. min. max. unit cl=2 10 10 10 10 ns tclk clk cycle time cl=3 6 7 7.5 8 ns tch clk high pulse width 2 2.5 2.5 3 ns tcl clk low pulse width 2 2.5 2.5 3 ns tt transition time of clk 1 10 1 10 1 10 1 10 ns tis input setup time (all inputs) 2 2.5 2.5 2.5 ns tih input hold time (all inputs) 1 1 1 1 ns trc row cycle time 60 63 67.5 70 ns trfc refersh cycle time 60 70 75 80 ns trcd row to column delay 18 20 20 20 ns tras row active time 42 100k 45 100k 45 100k 48 100k ns trp row precharge time 18 20 20 20 ns twr write recovery time 12 14 15 20 ns trrd act to act delay time 12 14 15 20 ns trsc mode register set cycle time 12 14 15 20 ns tref refresh interval time 64 64 64 64 ms clk dq 1.4v 1.4v any ac timing is referenced to the input signal passing throutg 1.4v
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 36 ? switching characteristics (vdd=vddq=3.30.3v,vss=vssq=0v,unless otherwise noted) limits -6 -7 -7.5 -8 symbol parameter min. max min. max min. max min. max. unit note cl=2 6 6 6 6 ns tac access time from clk cl=3 5 5.4 5.4 6 ns cl=2 3 3 3 3 ns toh output hold time from clk cl=3 2.5 2.7 3 3 ns tolz delay time, output low-impedance from clk 0 0 0 0 ns tohz delay time, output high-impedance from clk 2.5 5 2.7 5.4 3 5.4 3 6 ns *1 note: 1. if clock rising time is longer than 1ns,(tr/2-0.5ns) should be added to the parameter. output load condition output 50 [ 50pf vtt=+1.4 v z0=50 [ ac output load circuit clk 1.4v dq 1.4v clk 1.4v 1.4v dq trc toh tohz tolz
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 37 ? burst write (single bank) @bl=4 012345678910111213141516 clk /cs /ras /cas /we cke dqm x y x y x x a0-8 a10 x x a9,11 0 0 0 0 ba0,1 0 0 d0 d0 d0 d0 d0 d0 d0 d0 dq trc tras trp trcd trcd twr twr act#0 write#0 pre#0 act#0 write#0 pre#0 italic parameter indicates minimum case
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 38 ? burst write (multi bank) @bl=4 012345678910111213141516 clk trc /ras cke trp trcd trcd twr twr /cs trc tras /cas /we dqm x y y y x x a0-8 a10 x x a9,11 0 0 0 0 ba0,1 0 d0 d0 d0 d0 d0 d0 d0 d0 dq act#0 write#0 pre#0 act#0 write#0 pre#0 italic parameter indicates minimum case x x x x x x x 1 1 0 1 d1 d1 d1 d1 act#1 write a#1 (auto-precharge) act#1 trrd trcd
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 39 ? burst read (single bank) @bl=4 cl=2 /cs trc tras trp /cas cke dqm x y x x a0-8 a10 x x a9,11 0 0 ba0,1 dq act#0 read#0 pre#0 act#0 pre#0 italic parameter indicates minimum case 012345678910111213141516 clk /ras trcd trcd trcd /we y x 0 0 0 0 d0 d0 d0 d0 d0 d0 d0 d0 tras read#0
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 40 ? burst read (multiple bank) @bl=4 cl=2 012345678910111213141516 clk trc cke /cs trc tras /we dqm a0-8 a10 a9,11 ba0,1 dq trrd /cas trcd trcd act#0 reada#0 italic parameter indicates minimum case reada#1 act#1 trcd pre#0 act#0 read#0 act#1 /ras x y y x y x x x x x x x x x x 0 0 1 1 0 0 1 0 q0 q0 q0 q0 q1 q1 q1 q1 q0 q0 q0 q0
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 41 ? write interrupted by write @bl=4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs trrd trcd twr cke dqm a0-8 a10 a9,11 dq x x act#0 write#0 pre#0 italic parameter indicates minimum case x x write#0 interrupt same bank act#1 x y x y d0 d0 d0 d0 d0 d1 d1 d1 d0 d0 d0 d0 /ras /cas /we y y x x x ba0,1 0 0 0 1 1 0 0 1 write a#1 interrupt other bank write#0 interrupt other bank act#1
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 42 ? read interrupted by read @bl=4,cl=2 012345678910111213141516 clk /cs trrd trcd cke dqm a0-8 a10 a9,11 dq x x act#0 read#0 italic parameter indicates minimum case x x read#1 interrupt other bank act#1 x y x y /ras /cas /we y y x ba0,1 0 0 1 1 1 0 read a#1 interrupt same bank read#0 interrupt other bank act#1 x x 1 q0 q0 q0 q0 q0 trcd q0 q0 q1 q1 q1 q1 q1
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 43 ? write interrupted by read, read interrupted by write @bl=4,cl=2 012345678910111213141516 clk trcd cke dqm a0-8 a10 a9,11 dq x x act#0 act#1 italic parameter indicates minimum case read#1 write#0 x x y y /cas /we y ba0,1 0 1 1 0 1 write#1 pre#1 1 q1 q1 d1 d1 d1 d1 trcd x x d0 d0 /cs /ras trrd twr
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 44 ? write/read terminated by precharge @bl=4,cl=2 012345678910111213141516 clk trcd cke dqm a0-8 a10 a9,11 dq x x act#0 write#0 italic parameter indicates minimum case pre#0 terminate x y y /cas /we ba0,1 0 0 read#0 act#0 q0 q0 trcd /cs /ras x x x x x x 0 0 0 0 0 d0 d0 act#0 pre#0 terminate trc trp trp tras twr
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 45 ? write/read terminated by burst terminate @bl=4,cl=2 012345678910111213141516 clk /cs /ras cke trcd twr /cas /we dqm x y x a0-8 a10 x a9,11 0 0 ba0,1 d0 d0 d0 d0 d0 d0 dq act#0 write#0 term write#0 pre#0 italic parameter indicates minimum case 0 q1 q1 read#0 term y y 0 0
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 46 ? single write burst read @bl=4,cl=2 012345678910111213141516 clk /cs /ras cke trcd /cas /we dqm x y x a0-8 a10 x a9,11 0 0 ba0,1 d0 d0 d0 d0 d0 dq act#0 write#0 italic parameter indicates minimum case read#0 y 0
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 47 ? power-up sequesce and intialize 012345678910111213141516 clk /cs cke /ras trp /cas /we 200us trfc trfc trsc dqm a0-8 a10 a9,11 ba0,1 dq act#0 x ma x 0 x 0 0 0 nop power on mrs refa refa refa pre all minimum 8 refa cycles italic parameter indicates minimum case
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 48 ? auto refresh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 clk /cs /ras cke trp /cas dqm a0-8 a10 a9,11 ba0,1 d0 d0 d0 d0 dq pre all italic parameter indicates minimum case x y x x 0 0 prea write#0 act#0 trfc trcd /we
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 49 ? self refresh italic p arameter indicates minimum case 012345678910111213141516 clk /cs cke /ras trp /cas /we dqm a0-8 a10 a9,11 ba0,1 dq act#0 x x x 0 self refresh entry trfc pre all self refresh exit all banks must be idle before refs is issued
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 50 ? clk suspension @bl=4,cl=2 012345678910111213141516 clk /cs cke dqm x y x a0-8 a10 x a9,11 0 0 ba0,1 dq act#0 write#0 italic parameter indicates minimum case /ras trcd /cas /we y 0 d0 d0 d0 d0 q0 q0 q0 q0 read#0 internal clk suspended internal clk suspended
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 51 ? power down 0 1 2 3 4 5 6 7 8 9 10111213141516 clk /cs cke dqm a0-8 a10 a9,11 ba0,1 dq pre all /ras standby power down /cas /we act#0 x 0 x x active power down
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 52 ? package outline dimension 54 pin 400mil tsop ii package outline dimension
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 53 ? ordering information commercial temperature : part no. access time package ut52l0464mc-6 UT52L0864mc-6 ut52l1664mc-6 6ns 54 pin tsop ii ut52l0464mc-7 UT52L0864mc-7 ut52l1664mc-7 7ns 54 pin tsop ii ut52l0464mc-7.5 UT52L0864mc-7.5 ut52l1664mc-7.5 7.5ns 54 pin tsop ii ut52l0464mc-8 UT52L0864mc-8 ut52l1664mc-8 8ns 54 pin tsop ii extended temperature : part no. access time package ut52l0464mc-6e UT52L0864mc-6e ut52l1664mc-6e 6ns 54 pin tsop ii ut52l0464mc-7e UT52L0864mc-7e ut52l1664mc-7e 7ns 54 pin tsop ii ut52l0464mc-7.5e UT52L0864mc-7.5e ut52l1664mc-7.5e 7.5ns 54 pin tsop ii ut52l0464mc-8e UT52L0864mc-8e ut52l1664mc-8e 8ns 54 pin tsop ii
utron ut52l1664/0864/0464 rev. 1.4 64m(x16-bits / x8-bits / x4-bits)sdram utron technology inc. p90006 1f, no. 11, r&d rd. ii, science-based industrial park, hsinchu, taiwan, r. o. c. tel: 886-3-5777882 fax: 886-3-5777919 54 ? this page is left blank intentionally.

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